graph LR V0(V0 - PI/O) FF1(FF1) FF2(FF2) FF3(FF3) FF4(FF4) V0 -- "CP-3" --> FF1 FF1 -- "3" --> V0 V0 -- "CP-7" --> FF2 FF2 -- "6" --> V0 FF1 -- "CP-10" --> FF4 FF4 -- "8" --> FF1 FF1 -- "6" --> FF2 FF2 -- "CP-6" --> FF1 FF2 -- "6" --> FF3 FF3 -- "CP-6" --> FF2 FF3 -- "6" --> FF4 FF4 -- "CP-8" --> FF3 style V0 fill:#e1f5fe,stroke:#01579b,stroke-width:3px style FF1 fill:#fce4ec,stroke:#880e4f,stroke-width:3px style FF2 fill:#fce4ec,stroke:#880e4f,stroke-width:3px style FF3 fill:#fce4ec,stroke:#880e4f,stroke-width:3px style FF4 fill:#fce4ec,stroke:#880e4f,stroke-width:3px
graph TD subgraph "Type a: No delay can be inserted (Direct connection)" ui_a["ui"] -- "CP-4" --> uj_a["uj"] ui_a -- "1.5" --> uj_a end subgraph "Type b: ps, ph independently (Independent structure)" ui_b["ui"] -- "0" --> us_b(us) ui_b -- "0" --> uh_b(uh) us_b -- "CP-4" --> uj_b["uj"] uh_b -- "1.5" --> uj_b end subgraph "Type c: ps = ph (Shared path segment)" ui_c["ui"] -- "0" --> us_c(us=uh) us_c -- "CP-4" --> uj_c["uj"] us_c -- "1.5" --> uj_c end subgraph "Type d: ps >= ph (Hierarchical containment)" ui_d["ui"] -- "0" --> us_d(us) ui_d -- "0" --> uh_d(uh) us_d -- "0" --> uh_d us_d -- "CP-4" --> uj_d["uj"] uh_d -- "1.5" --> uj_d end style ui_a fill:#e3f2fd,stroke:#1565c0,stroke-width:3px style uj_a fill:#ffccbc,stroke:#bf360c,stroke-width:3px style ui_b fill:#e3f2fd,stroke:#1565c0,stroke-width:3px style us_b fill:#fff9c4,stroke:#f57f17,stroke-width:3px style uh_b fill:#fff9c4,stroke:#f57f17,stroke-width:3px style uj_b fill:#ffccbc,stroke:#bf360c,stroke-width:3px style ui_c fill:#e3f2fd,stroke:#1565c0,stroke-width:3px style us_c fill:#fff9c4,stroke:#f57f17,stroke-width:3px style uj_c fill:#ffccbc,stroke:#bf360c,stroke-width:3px style ui_d fill:#e3f2fd,stroke:#1565c0,stroke-width:3px style us_d fill:#fff9c4,stroke:#f57f17,stroke-width:3px style uh_d fill:#fff9c4,stroke:#f57f17,stroke-width:3px style uj_d fill:#ffccbc,stroke:#bf360c,stroke-width:3px
graph TD A[Circuit Design] --> B{Multi-Corner STA}; B --> C[Timing Info. Extraction]; C --> D[Path Relationship Analysis]; D --> E[TCG Enhancement]; E --> F{Build Timing Constraint Graph}; F --> G{Detect Negative Cycles?}; G -- Yes --> H[TCP Infeasible]; H --> I["Update T_low, TCP = (T_high + TCP)/2"]; G -- No --> J{Feasible Timing Solution?}; J -- No --> K["Dual Decomposition Delay Padding Solver (Multi-Corner)"]; K --> J; J -- Yes --> L{T_high - T_low < ฮต?}; L -- No --> M["Update T_high, TCP = (T_low + TCP)/2"]; L -- Yes --> N[Optimal TCP Found]; I --> F; M --> F; style A fill:#e3f2fd,stroke:#1565c0,color:#2e3440,stroke-width:3px style B fill:#ffcdd2,stroke:#c62828,color:#2e3440,stroke-width:3px style C fill:#fff3e0,stroke:#e65100,color:#2e3440,stroke-width:3px style D fill:#f3e5f5,stroke:#7b1fa2,color:#2e3440,stroke-width:3px style E fill:#f3e5f5,stroke:#7b1fa2,color:#2e3440,stroke-width:3px style F fill:#ffcdd2,stroke:#c62828,color:#2e3440,stroke-width:3px style G fill:#ffcdd2,stroke:#c62828,color:#2e3440,stroke-width:3px style H fill:#fce4ec,stroke:#ad1457,color:#2e3440,stroke-width:3px style I fill:#fff3e0,stroke:#e65100,stroke-width:3px style J fill:#ffcdd2,stroke:#c62828,color:#2e3440,stroke-width:3px style K fill:#f3e5f5,stroke:#7b1fa2,color:#2e3440,stroke-width:3px style L fill:#ffcdd2,stroke:#c62828,color:#2e3440,stroke-width:3px style M fill:#fff3e0,stroke:#e65100,stroke-width:3px style N fill:#c8e6c9,stroke:#2e7d32,color:#2e3440,stroke-width:3px