layout: true class: typo, typo-selection --- class: nord-dark, middle, center # Lecture 4a: Robust Analog Circuit Sizing Under Process Variations @luk036 ๐จโ๐ป ยท 2026 ๐ --- ### ๐ Abstract This lecture focuses on robust sizing of analog circuits under process variations at advanced nodes. Key topics include: - ๐๏ธ Challenges in 20nm analog design (double-patterning, layout effects, FinFET/GAA transistors) - ๐ก๏ธ Designing for robustness against process variations - โ๏ธ Analog circuit sizing problem formulation - ๐ Emerging CAD approaches: - Knowledge-based methods - Optimization-based techniques - ๐งฎ Robust geometric programming using: - Affine arithmetic - Ellipsoid method - ๐ CMOS two-stage op-amp design case study --- ### ๐ Keywords .pull-left[ - ๐๏ธ Analog circuit ๆจกๆ็ต่ทฏ - ๐ก๏ธ Design for robustness ้ฒๆฃๆง่ฎพ่ฎก - โ ๏ธ Worst-case scenarios ๆๅๆ ๆฏ - โ Affine arithmetic ไปฟๅฐ่ฟ็ฎ - ๐ฅ Convex programming ๅธ่งๅ - ๐ Geometric programming ๅ ไฝ่งๅ - โ Posynomial ๆญฃ้กนๅผ (Positive + polynomial) - ๐ซ Ellipsoid method ๆคญ็ๆณ ] .pull-right[  ] --- ### Overview ๐ - ๐๏ธ 20nm Analog Design Challenges - ๐ Design for Variability - ๐ก๏ธ Design for Robustness - โ๏ธ Analog Sizing Formulation - ๐ก๏ธ Robust Geometric Programming - โ Affine Arithmetic Methods - ๐ Design Examples --- ### ๐ฌ Introduction: Cost Comparison | Costs | 28nm | 20nm | | ------------ | --------- | ----------- | | Fab Costs | 3B | 4B - 7B | | Process R&D | 1.2B | 2.1B - 3B | | Mask Costs | 2M - 3M | 5M - 8M | | Design Costs | 50M - 90M | 120M - 500M | : Fab, process, mask, and design costs are much higher at 20nm (IBS, May 2011) --- ### ๐๏ธ Challenges at 20nm - ๐จ Double-patterning requirements - ๐ Layout-dependent effects - ๐ New local interconnect layers - ๐ >5,000 design rules - โ ๏ธ Device variation and sensitivity - ๐๏ธ FinFET/GAA transistors --- ### ๐จ Double Patterning  --- ### โ ๏ธ Overlay Error (Mask Shift) - Parasitic matching becomes very challenging  --- ### ๐ Layout-Dependent Effects | Effect | >40nm | 40nm | โฅ28nm | |---------------------------------|:-----:|:----:|:-----:| | Well Proximity Effect (WPE) | x | x | x | | Poly Spacing Effect (PSE) | | x | x | | Length of Diffusion (LOD) | x | x | x | | OD to OD Spacing Effect (OSE) | | x | x | --- ### ๐ New Local Interconnect Layers  --- ### ๐๏ธ FinFET Transistors  --- ### ๐๏ธ Gate-All-Around Transistors  --- ### ๐ก๏ธ Design for Robustness Key considerations for analog circuits: - Process variations are inherent in manufacturing - Variations caused by: - ๐ก๏ธ Temperature - โก Voltage - ๐ญ Manufacturing tolerances - Must include process variations in specifications --- ### ๐ Basic Design Flow  --- ### ๐ Top-down Design Phases  --- ### ๐ Analog Synthesis Flow  --- ### โ๏ธ Analog Circuit Sizing Problem **Definition**: Given circuit topology, specifications and technology, find design variables that: - Meet all specifications - Optimize circuit performance **Challenges**: - ๐๏ธ High degrees of freedom - โ ๏ธ Performance sensitivity to variations --- ### ๐ป Main CAD Approaches .pull-left[ **Knowledge-based**: - Circuit understanding - Design heuristics ] .pull-right[ **Optimization-based**: - Equation-based: - Circuit equations - Numerical solvers - Simulation-based: - Circuit simulation ] *Practical designs mix these approaches* --- ### ๐ Geometric Programming (GP) Emerging technique for analog design: - Solves robust GP problems using: - ๐ซ Ellipsoid method - โ Affine arithmetic - Provides mathematical guarantees - Enables formal optimization --- ### ๐ก๏ธ Robust Optimization Under Process Variation .mermaid[ <pre> graph TD A[Process Variations] --> B[Affine Arithmetic] B --> C[Worst-Case Bounds] C --> D[Robust GP Formulation] D --> E[Ellipsoid Method] E --> F[Optimal Robust Sizing] style A fill:#f44336 style B fill:#ff9800 style C fill:#ff9800 style D fill:#2196f3 style E fill:#9c27b0 style F fill:#4caf50 </pre> ] --- class: nord-dark, middle, center .pull-left[ # Q&A ๐ค ] .pull-right[  ]