layout: true class: typo, typo-selection --- count: false class: nord-dark, middle, center # โ Lecture 05a - Clock Skew Scheduling Under Process Variations @luk036 ๐จโ๐ป ยท 2026 ๐ --- ### ๐ Abstract The main topic of the lecture is clock skew scheduling under process variations. The lecture discusses various techniques and methods for optimizing clock skew to improve circuit performance or minimize timing failures. The lecture begins with an overview of the problem and background of clock skew scheduling. It then explains the concept of clock skew and the difference between zero skew and useful skew designs. The importance of meeting timing constraints, such as setup time and hold time, is discussed, along with the potential problems that can occur if these constraints are violated. The lecture presents various approaches to clock skew scheduling, such as traditional scheduling, yield-driven scheduling, and minimum cost-to-time ratio cycle formulation. It also examines various methods for finding the optimal clock period and the corresponding skew schedule, including linear programming and the use of the Bellman-Ford algorithm. --- ### ๐ Abstract (II) .font-sm.mb-xs[ The lecture goes on to discuss primitive solutions and their shortcomings, such as pre-allocating timing margins and using the Least Center Error Square (LCES) problem formulation. The lecture also introduces more advanced techniques such as slack maximization (EVEN) and prop-based methods that distribute slack along the most timing-critical cycle based on Gaussian models. The drawbacks of these methods are highlighted, particularly their assumptions about gate delay distributions. Finally, statistical static timing analysis (SSTA) and the use of statistical methods to account for process variations are discussed. The concept of the most critical cycle is introduced, and the lecture provides experimental results to demonstrate the effectiveness of various clock skew scheduling techniques. ] --- ### ๐ Keywords .pull-left[ - Static timing analysis, ้ๆๆถๅบๅๆ - Statistical STA ็ป่ฎก้ๆๆถๅบๅๆ - Clock skew ๆถ้ๅๅทฎ/ๅๆ - Zero skew design ้ถๅๅทฎ่ฎพ่ฎก - Critical paths ๅ ณ้ฎ่ทฏๅพ - Negative slack ่ดๆถๅบ่ฃ้ - Useful skew design ๆๆๅๅทฎ่ฎพ่ฎก - Critical cycles ๅ ณ้ฎ็ฏ - Negative cycles ่ด็ฏ - Clock skew scheduling โ (CSS) ๆถ้ๅๅทฎๅฎๆ/่งๅ ] .pull-right[  ] --- ### ๐ Overview - Background - Problem formulation - Traditional clock skew scheduling โ - Yield-driven clock skew scheduling โ - Minimum cost-to-time ratio cycle formulation --- .mermaid[ <pre> graph TD A[Circuit Netlist] --> B[Timing Analysis] B --> C[Skew Assignment] C --> D{Constraints Met?} D -- Yes --> E[Optimize Clock Period] D -- No --> C E --> F[Yield-Driven Schedule] style A fill:#c8e6c9,stroke:#2e7d32,stroke-width:3px style B fill:#fff3e0,stroke:#e65100,stroke-width:3px style C fill:#e3f2fd,stroke:#1565c0,stroke-width:3px style D fill:#f3e5f5,stroke:#7b1fa2,stroke-width:3px style E fill:#ffcdd2,stroke:#c62828,stroke-width:3px style F fill:#c8e6c9,stroke:#2e7d32,stroke-width:3px </pre> ] --- class: nord-light, middle, center ## ๐ฐ๏ธ Traditional Clock Skew Scheduling --- ### ๐ Sequential Logic - Local data path  --- ### ๐ Sequential Logic (cont'd) - Graph  --- ### โฑ๏ธ Clock Skew .pull-left[ - ${\color{red}T_\text{skew}}(i,f) = {\color{red}t_i} - {\color{red}t_f}$, where - ${\color{red}t_i}$: clock signal delay at the initial register - ${\color{red}t_f}$: clock signal delay at the final register - We are not interested in the absolute time. Why? ] .pull-right[  ] --- ### ๐ Timing Constraint - Setup time constraint $${\color{red}T_\text{skew}}(i,f) \le {\color{darkblack}T_\text{CP}} - {\color{purple}D}_{if} - {\color{blue}T_\text{setup}} = {\color{red}u}_{if}$$ While this constraint destroyed, cycle time violation (zero clocking) occurs. - Hold time constraint $${\color{red}T_\text{skew}}(i,f) \ge {\color{blue}T_\text{hold}} - {\color{purple}d}_{if} = {\color{red}l}_{if}$$ While this constraint destroyed, race condition (double clocking) occurs. --- ### โ๏ธ Zero Skew vs. Useful Skew - Zero skew (${\color{red}t_i} = {\color{red}t_f}$) : Relatively easy to implement. - Useful skew. Improve: - The performance of the circuit by permitting a higher maximum clock frequency, or - The safety margins of the clock skew within the permissible ranges. - Max./min. path delays are got from static timing analysis (STA). --- ### ๐ธ๏ธ Timing Constraint Graph - Create a graph by - replacing the hold time constraint with a *h-edge* with cost $-({\color{blue}T_\text{hold}} - {\color{purple}d}_{ij})$ from $\text{FF}_i$ to $\text{FF}_j$, and - replacing the setup time constraint with an s-edge with cost ${\color{darkblack}T_\text{CP}} - {\color{purple}D}_{ij} - {\color{blue}T_\text{setup}}$ from $\text{FF}_j$ to $\text{FF}_i$. - Two sets of constraints stemming from clock skew definition: - The sum of skews for paths having the same starting and ending flip-flop to be the same; - The sum of clock skews of all cycles to be zero --- ### ๐ธ๏ธ Timing Constraint Graph (TCG)  --- ### ๐ธ๏ธ Timing Constraint Graph (TCG) .pull-left[ Assume ${\color{blue}T_\text{setup}} = {\color{blue}T_\text{hold}}$ = 0 Clock period ${\color{darkblack}T_\text{CP}}$ is feasible if and only if current graph contains no negative cost cycles. ] .pull-right[  ] --- ### ๐ฏ Minimize Clock Period - Linear programming (LP) formulation $$\begin{array}{ll} \text{minimize} & {\color{darkblack}T_\text{CP} } \\ \text{subject to} & {\color{red}l}_{ij} \leq {\color{red}t_i} - {\color{red}t_j} \leq {\color{red}u}_{ij} \end{array}$$ where $\text{FF}_i$ and $\text{FF}_j$ are sequential adjacent - The above constraint condition is so-called **system of difference constraints** (see Introduction to Algorithms, MIT): - ๐ Note: easy to check if a feasible solution exists by detecting negative cycle using for example Bellman-Ford algorithm. --- ### ๐ฃ๏ธ Basic Bellman-Ford Algorithm .font-sm.mb-xs[ ```matlab function BellmanFord(list vertices, list edges, vertex source) // Step 1: initialize graph for each vertex i in vertices: if i is source then u[i] := 0 else u[i] := inf predecessor[i] := null // Step 2: relax edges repeatedly for i from 1 to size(vertices)-1: for each edge (i, j) with weight d in edges: if u[j] > u[i] + d[i,j]: u[j] := u[i] + d[i,j] predecessor[j] := i // Step 3: check for negative-weight cycles for each edge (i, j) with weight d in edges: if u[j] > u[i] + d[i,j]: error "Graph contains a negative-weight cycle" return u[], predecessor[] ``` ] --- ### โ ๏ธ Problems with Bellman-Ford Algorithm - The algorithm is originally used for finding the shortest paths. - Detecting negative cycle is just a side product of the algorithm. - The algorithm is simple, but... - detects negative cycle at the end only. - has to compute all `d[i,j]`. - Restart the initialization with `u[i] := inf`. - requests the input graph must have a source node. Various improvements have been proposed extensively. --- ### ๐ฏ Minimize Clock Period (I) - Fast algorithm for solving the LP: - Use binary search method for finding the minimum clock period. - In each iteration, Bellman-Ford algorithm is called to detect if the timing constraint graph contains negative weighted edge cycle. - ๐ Note: Originally Bellman-Ford algorithm is used to find a shortest-path of a graph. --- ### ๐ฏ Minimize Clock Period (II) - When the optimal clock period is solved, the corresponding skew schedule is got simultaneously. - However, many skew values are on the bounds of feasible range.  --- class: nord-light, middle, center ## ๐พ Yield-Driven Clock Skew Scheduling --- ### ๐พ Yield-Driven Clock Skew Scheduling - When process variations increase more and more, timing-failure-induced yield loss becomes a significant problem. - Yield-driven Clock Skew Scheduling becomes important. - Primary goal of this scheduling is to minimize the yield loss instead of minimizing the clock period. --- ### ๐ Timing Yield Definition - The circuit is called functionally correct if all the setup- and hold-time constraints are satisfied under a group of determinate process parameters. - Timing Yield = (functional correct times) / sample number \* 100% --- ### ๐งฉ Primitive Solution (1) - Pre-allocate timing margins (usually equivalent to maximum timing uncertainty) at both ends of the FSR's (Feasible Skew Region). $${\color{red}l}_{ij} \leq {\color{red}s}_{ij} \leq {\color{red}u}_{ij} \implies {\color{red}l}_{ij} + {\color{blue}\Delta d} \leq {\color{red}s}_{ij} \leq {\color{red}u}_{ij} - {\color{blue}\Delta d}$$ - Then perform clock period optimization. --- ### โ ๏ธ Problems with This Method - The maximum timing uncertainty is too pessimistic. Lose some performance; - ${\color{blue}\Delta d}$ is fixed; it does not consider data path delay differences between cycle edges. --- ### ๐ References (1) - "Clock skew optimization", IEEE Trans. Computers, 1990 - "A graph-theoretic approach to clock skew optimization", ISCAS'94 - "Cycle time and slack optimization for VLSI-chips", ICCAD'99 - "Clock scheduling and clocktree construction for high performance Asics", ICCAD'03 - "ExtensiveSlackBalance: an Approach to Make Front-end Tools Aware of Clock Skew Scheduling", DAC'06 --- ### ๐งฉ Primitive Solution (2) - Formulate as LCES (Least Center Error Square) problem - A simple observation suggests that, to maximize slack, skew values should be chosen as close as possible to the middle points of their FSR's. $${\color{red}l}_{ij} + {\color{green}lm}_k ({\color{red}u}_{ij} - {\color{red}l}_{ij}) \leq {\color{red}s}_{ij} \leq {\color{red}u}_{ij} - {\color{green}um}_k ({\color{red}u}_{ij} - {\color{red}l}_{ij})$$ $$\begin{array}{ll} \text{minimize} & \sum_k (0.5 - \min({\color{green}lm}_k, {\color{green}um}_k) )^2 \\ \text{subject to} & 0 \leq {\color{green}lm}_k \leq 0.5 \\ & 0 \leq {\color{green}um}_k \leq 0.5 \end{array}$$ --- ### ๐ References (2) - Graph-based algorithm - (J. L. Neves and E. G. Friedman, "Optimal Clock Skew Scheduling Tolerant to Process Variations", DAC'96) - Quadratic Programming method - (I. S. Kourtev and E. G. Fredman, "Clock skew scheduling โ for improved reliability via quadratic programming", ICCAD'99) Shortcoming: might reduce some slacks to be zero to minimum **total** CES. This is not optimal for yield. --- ### ๐งฉ Primitive Solution (3) - Incremental Slack Distribution - (Xinjie Wei, Yici CAI and Xianlong Hong, "Clock skew scheduling โ under process variations", ISQED'06) - Advantage: check all skew constraints - Disadvantage: didn't take the path delay difference into consideration --- ### ๐ Minimum Mean Cycle Based - **Even**: solve the slack optimization problem using a minimum mean cycle formulation. - **Prop**: distribute slack along the most timing-critical cycle proportional to path delays - **FP-Prop**: use sensitizable-critical-path search algorithm for clock skew scheduling. --- ### โ๏ธ Slack Maximization (EVEN) - Slack Maximization Scheduling $$\begin{array}{ll} \text{maximize} & {\color{green}\beta} \\ \text{subject to} & {\color{red}t_j} - {\color{red}t_i} \leq {\color{darkmagenta}\mu_{ij}} - {\color{green}\beta} \end{array}$$ - Equivalent to the so-called minimum mean cycle problem (MMC), where $${\color{green}\beta}^* = \frac{1}{|{\color{lime}C}|} \sum\limits_{(i,j)\in {\color{lime}C}} {\color{darkmagenta}\mu_{ij}}$$ ${\color{lime}C}$: critical cycle (first negative cycle) - Can be solved efficiently by the above method. --- ### ๐ Even - Iterative Slack Optimization - Identify the circuit's most timing-critical cycle, - Distribute the slack along the cycle, - Freeze the clock skews on the cycle, and - Repeat the process iteratively. --- ### ๐ฏ Identify the Timing-Critical Cycle .pull-left[ 1. Identify the circuit's most timing-critical cycle 2. Solve the minimum mean-weight cycle problem by - Karp's algorithm - A. Dasdan and R.K.Gupta, "Faster Maximum and Minimum Mean Cycle Algorithms for System-Performance", TCAD'98. ] .pull-right[  ] --- ### ๐ค Distribute the Slack .pull-left[ Distribute the slack evenly along the most timing-critical cycle.  ] .pull-right[  ] --- ### ๐ง Freeze the Clock Skews (I) .pull-left[ Replace the critical cycle with super vertex.  ] .pull-right[  ] --- ### ๐ง Freeze the Clock Skews (II) .pull-left[ To determine the optimal slacks and skews for the rest of the graph, we replace the critical cycle with super vertex.  ] .pull-right[  ] --- ### ๐ Repeat the Process (I) .pull-left[  ] .pull-right[  ] --- ### ๐ Repeat the Process (II) .pull-left[  ] .pull-right[  ] --- ### ๐ Final Result .pull-left[ - ${\color{blue}\text{Skew}}_{12}$ = 0.75 - ${\color{blue}\text{Skew}}_{23}$ = -0.25 - ${\color{blue}\text{Skew}}_{31}$ = -0.5 - ${\color{blue}\text{Slack}}_{12}$ = 1.75 - ${\color{blue}\text{Slack}}_{23}$ = 1.75 - ${\color{blue}\text{Slack}}_{31}$ = 1 ] .pull-right[  ] where ${\color{blue}\text{Slack}}_{ij} = {\color{darkblack}T_\text{CP}} - {\color{purple}D}_{ij} - {\color{blue}T_\text{setup}} - {\color{blue}\text{Skew}}_{ij}$ --- ### โ ๏ธ Problems with Even - Assume all variances are the same. - However, the timing uncertainty of a long combinational path is usually larger than that of a shorter path. - Therefore, the even slack distribution along timing-critical cycles performed by **Even** is not optimal for yield if data path delays along the cycles are different. --- ### ๐ Prop-Based on Gaussian Model (I) - Assuming there are $n$ gates with delay $N({\color{darkmagenta}\mu},{\color{coral}\sigma}^2)$ in a path, then this path delay is $N(n{\color{darkmagenta}\mu},n{\color{coral}\sigma}^2)$ - Distribute slack along the most timing-critical cycle, according to the square root of each edge's path delays (???). - To achieve this, update the weights of s-edges and h-edges: $$\begin{array}{ll} {\color{darkblack}T_\text{CP}} - ({\color{purple}D}_{ij} + {\color{blue}\alpha} \sqrt{{\color{purple}D}_{ij} } {\color{coral}\sigma}) - {\color{blue}T_\text{setup}} \\ -{\color{blue}T_\text{hold}} + ({\color{purple}d}_{ij} - {\color{blue}\alpha} \sqrt{{\color{purple}d}_{ij} } {\color{coral}\sigma}) \end{array}$$ where ${\color{blue}\alpha}$ ensures a minimum timing margin for each timing constraint. --- ### ๐ Prop-Based on Gaussian Model (II) - Given a specific clock period ${\color{darkblack}T_\text{CP}}$, we gradually increase ${\color{blue}\alpha}$ and use the Bellman-Ford algorithm to detect whether it is still feasible. - After finding the maximum ${\color{blue}\alpha}$, the edges along the most timing-critical cycle will have slacks equal to the pre-allocated timing margins. - Many edges in a circuit have sufficiently large slack. Therefore, we can perform proportional slack distribution only for the most timing-critical cycle. Assign the rest of skews using **Even**. --- ### โ ๏ธ Problems with Prop - Assume all gate delay has the same distribution. - Not justify using the square root of path delay for timing margin. --- ### ๐ค๏ธ FP-Prop (I)  False path --- ### ๐ค๏ธ FP-Prop (II) - If we do not consider false path, some non timing-critical cycles become timing-critical. Then, more slacks are distributed to these cycles, but the slacks in actually timing-critical cycles are not sufficient. As a result, the overall timing yield decreases. --- ### โ ๏ธ Problems with FP-Prop - Same problems as Prop --- ### ๐งช Experimental Results  --- class: nord-light, middle, center ## ๐ Statistical Timing Analysis --- ### ๐ Statistical Method - Setup time constraint $${\color{red}T_\text{skew}}(i,f) \le {\color{darkblack}T_\text{CP}} - {\color{purple}\tilde{D}}_{if} - {\color{blue}T_\text{setup}}$$ - Hold time constraint $${\color{red}T_\text{skew}}(i,f) \ge {\color{blue}T_\text{hold}} - {\color{purple}\tilde{d}}_{if}$$ where ${\color{purple}\tilde{D}}_{if} \text{ and } {\color{purple}\tilde{d}}_{if}$ are random variable under process variations. --- ### ๐ Statistical TC Graph  After SSTA, edge weight is represented as a pair of value (mean, variance). --- ### ๐ฏ Most Critical Cycle - Traditional criteria: minimum mean cycle $$\min_{{\color{lime}C} \in {\color{lime}\mathcal{C}} } \frac{\sum_{(i,j)\in {\color{lime}C}} {\color{darkmagenta}\mu_{ij}} }{|{\color{lime}C}|}$$ - New criteria: $$\min_{{\color{lime}C} \in {\color{lime}\mathcal{C}} } \frac{\sum_{(i,j)\in {\color{lime}C}} {\color{darkmagenta}\mu_{ij}} }{\sum_{(i,j)\in {\color{lime}C}} {\color{coral}\sigma_{ij}} }$$ (We show the correctness later) --- ### โ๏ธ Slack Maximization (C-PROP) - Slack Maximization Scheduling $$\begin{array}{ll} \text{maximize} & {\color{coral}\beta} \\ \text{subject to} & {\color{red}t_j} - {\color{red}t_i} \leq {\color{darkmagenta}\mu_{ij}} - {\color{coral}\sigma_{ij}} {\color{coral}\beta} \end{array}$$ - Equivalent to the *minimum cost-to-time ratio cycle* problem (MMC), where: - ${\color{coral}\beta}^* = \frac{\sum_{(i,j)\in {\color{lime}C}} {\color{darkmagenta}\mu_{ij}} }{\sum_{(i,j)\in {\color{lime}C}} {\color{coral}\sigma_{ij}} }$ - ${\color{lime}C}$: critical cycle (first negative cycle) --- ### ๐ฎ Probability Observation - Prob(timing failure) turns out to be an Error function that solely depends on this ratio. Therefore, it is justified to use this ratio as critical criteria. --- ### ๐ Whole Flow - After determining the clock arrival time at each vertex in the most critical cycle, the cycle is replaced with a super vertex ${\color{salmon}v}'$. - In-edge $({\color{salmon}u}, {\color{salmon}v})$ from outside vertex ${\color{salmon}u}$ to cycle member ${\color{salmon}v}$ is replaced by an in-edge $({\color{salmon}u}, {\color{salmon}v}')$ with weight mean ${\color{darkmagenta}\mu}({\color{salmon}u}, {\color{salmon}v}) - {\color{red}T_v}$. - Out-edge $({\color{salmon}v}, {\color{salmon}u})$ is replaced by out-edge $({\color{salmon}v}', {\color{salmon}u})$ with weight mean ${\color{darkmagenta}\mu}({\color{salmon}v}, {\color{salmon}u}) + {\color{red}T_v}$. However, the variance of the edge weight is not changed. And parallel edges can be remained. - Repeat the process iteratively until the graph is reduced to a single super vertex, or the edges number is zero. --- ### ๐๏ธ Data Structure  Final ${\color{red}T_1} = {\color{red}T_1} + {\color{red}T_7} +{\color{red}T_9}$ --- ### ๐ Advantages of This Method - Justified by probability observation. - Fast algorithm exists for minimum cost-to-time ratio cycle problem. - Reduce to Even when all variances are equal. - When a variance tends to zero, it makes sense that only minimal slack is assigned to this variable, and hence others can be assigned more. --- ### ๐ Results \ --- ### ๐ Main Reference - Jeng-Liang Tsai, Dong Hyum Baik, Charlie Chung-Ping Chen, and Kewal K. Saluja, "Yield-Driven, False-Path-Aware Clock Skew Scheduling", IEEE Design & Test of Computers, May-June 2005 --- ### ๐๏ธ Backup ``` {.terminal} > pandoc -t beamer css.md beamer.yaml -o css.pdf ``` --- count: false class: nord-dark, middle, center .pull-left[ ## Q&A ๐ค ] .pull-right[  ]