graph LR A[Performance\nGoals] --> B[Nanometer\nLimits] B --> C[Power\nDensity] C --> D[Dark\nSilicon] D --> E[Approximate\nComputing] style A fill:#e3f2fd,stroke:#1565c0,stroke-width:3px style B fill:#fff9c4,stroke:#f57f17,stroke-width:3px style C fill:#fff9c4,stroke:#f57f17,stroke-width:3px style D fill:#ffcdd2,stroke:#c62828,stroke-width:3px style E fill:#c8e6c9,stroke:#2e7d32,stroke-width:3px
graph LR A[Approximate\nComputing] --> B[Multimedia] A --> C[Recognition] A --> D[Classification] A --> E[Machine\nLearning] style A fill:#e3f2fd,stroke:#1565c0,stroke-width:3px style B fill:#c8e6c9,stroke:#2e7d32,stroke-width:3px style C fill:#c8e6c9,stroke:#2e7d32,stroke-width:3px style D fill:#c8e6c9,stroke:#2e7d32,stroke-width:3px style E fill:#c8e6c9,stroke:#2e7d32,stroke-width:3px
graph LR A[Partial Product\nGeneration] --> B[Partial Product\nReduction] B --> C[Final\nAddition] style A fill:#e3f2fd,stroke:#1565c0,stroke-width:3px style B fill:#fff9c4,stroke:#f57f17,stroke-width:3px style C fill:#c8e6c9,stroke:#2e7d32,stroke-width:3px
graph TD A[Approximate Circuit\nDesign Methodologies] --> B[Voltage\nOverscaling] A --> C[Redesigning\nLogic Circuits] A --> D[Simplification\nAlgorithms] A --> E[Hybrid\nApproaches] style A fill:#e3f2fd,stroke:#1565c0,stroke-width:3px style B fill:#ffcdd2,stroke:#c62828,stroke-width:3px style C fill:#fff9c4,stroke:#f57f17,stroke-width:3px style D fill:#fff9c4,stroke:#f57f17,stroke-width:3px style E fill:#c8e6c9,stroke:#2e7d32,stroke-width:3px
graph TD A[Accuracy] --> D[Design\nTrade-offs] B[Performance] --> D C[Power] --> D E[Area] --> D style A fill:#e3f2fd,stroke:#1565c0,stroke-width:3px style B fill:#c8e6c9,stroke:#2e7d32,stroke-width:3px style C fill:#ffcdd2,stroke:#c62828,stroke-width:3px style E fill:#fff9c4,stroke:#f57f17,stroke-width:3px style D fill:#f3e5f5,stroke:#7b1fa2,stroke-width:3px
graph LR A[Error Metric\nEvaluation] --> B[Simulation] A --> C[Analytical] A --> D[BDD-based] A --> E[SAT\nSolvers] style A fill:#e3f2fd,stroke:#1565c0,stroke-width:3px style B fill:#fff9c4,stroke:#f57f17,stroke-width:3px style C fill:#fff9c4,stroke:#f57f17,stroke-width:3px style D fill:#ffcdd2,stroke:#c62828,stroke-width:3px style E fill:#c8e6c9,stroke:#2e7d32,stroke-width:3px
graph LR A[Analyze\nApplication] --> B[Specify QoS\n& Error Metrics] B --> C[Identify\nNon-critical Tasks] C --> D[Map Approx HW\nto Program Parts] style A fill:#e3f2fd,stroke:#1565c0,stroke-width:3px style B fill:#fff9c4,stroke:#f57f17,stroke-width:3px style C fill:#fff9c4,stroke:#f57f17,stroke-width:3px style D fill:#c8e6c9,stroke:#2e7d32,stroke-width:3px
graph LR A[Approximate\nMultipliers] --> B[Significant\nEfficiency Gains] B --> C[Minimal\nAccuracy Loss] C --> D[Design, Evaluation &\nApplication Challenges] style A fill:#e3f2fd,stroke:#1565c0,stroke-width:3px style B fill:#c8e6c9,stroke:#2e7d32,stroke-width:3px style C fill:#c8e6c9,stroke:#2e7d32,stroke-width:3px style D fill:#ffcdd2,stroke:#c62828,stroke-width:3px