graph TD subgraph "Liberty .lib File" L[Library] --> H[Header: technology, units, PVT] L --> OC["operating_conditions (typical)"] L --> T["lu_table_template (delay_2x2)"] L --> C1["cell (AND2_X1) π’"] L --> C2["cell (DFF_X1) π΅"] L --> C3["cell (INV_X1) π "] C1 --> P1["pin (A) β‘οΈ"] C1 --> P2["pin (B) β‘οΈ"] C1 --> P3["pin (Z) β¬ οΈ"] P3 --> T1["timing ()"] T1 --> CR["cell_rise (table)"] T1 --> RT["rise_transition (table)"] end style L fill:#e8eaf6,stroke:#283593,color:#2e3440,stroke-width:3px style H fill:#e8eaf6,stroke:#283593,color:#2e3440,stroke-width:3px style C1 fill:#c8e6c9,stroke:#2e7d32,color:#2e3440,stroke-width:3px style C2 fill:#e3f2fd,stroke:#1565c0,color:#2e3440,stroke-width:3px style C3 fill:#fff3e0,stroke:#e65100,color:#2e3440,stroke-width:3px
graph LR subgraph "Liberty Parser Data Model" direction LR G[Group] --> GN["group_name: str"] G --> GA["args: list[str]"] G --> GAT["attributes: list[Attribute]"] G --> GG["groups: list[Group] β recursive!"] GAT --> AT1["Attribute: name + value"] AT1 --> AT1V["value: EscapedString | list | float | int"] end subgraph "Timing Table Access" direction LR T["timing() group"] --> TG["get_groups('cell_rise')"] TG --> CR["cell_rise subgroup"] CR --> V["get_array('values')"] V --> NP["NumPy ndarray β "] end style G fill:#e8eaf6,stroke:#283593,color:#2e3440,stroke-width:3px style GN fill:#e8eaf6,stroke:#283593,color:#2e3440,stroke-width:3px style GA fill:#e8eaf6,stroke:#283593,color:#2e3440,stroke-width:3px style GAT fill:#e8eaf6,stroke:#283593,color:#2e3440,stroke-width:3px style GG fill:#fff3e0,stroke:#e65100,color:#2e3440,stroke-width:3px style T fill:#c8e6c9,stroke:#2e7d32,color:#2e3440,stroke-width:3px style CR fill:#c8e6c9,stroke:#2e7d32,color:#2e3440,stroke-width:3px style V fill:#e3f2fd,stroke:#1565c0,color:#2e3440,stroke-width:3px style NP fill:#ffcdd2,stroke:#c62828,color:#2e3440,stroke-width:3px
flowchart LR V["Verilog (.v)"] --> Y["Yosys\n synthesis"] Y --> J["JSON\n netlist"] J --> E["Cell type\n extraction"] E --> L["Liberty\n .lib file"] L --> C["convert-lib-to-json\nskill"] C --> J2["JSON + Schema\n validation β "] style V fill:#fff3e0,stroke:#e65100,color:#2e3440,stroke-width:3px style Y fill:#e3f2fd,stroke:#1565c0,color:#2e3440,stroke-width:3px style J fill:#c8e6c9,stroke:#2e7d32,color:#2e3440,stroke-width:3px style E fill:#f3e5f5,stroke:#7b1fa2,color:#2e3440,stroke-width:3px style L fill:#ffcdd2,stroke:#c62828,color:#2e3440,stroke-width:3px style C fill:#e3f2fd,stroke:#1565c0,color:#2e3440,stroke-width:3px style J2 fill:#c8e6c9,stroke:#2e7d32,color:#2e3440,stroke-width:3px
flowchart LR RTL["RTL Verilog\nmy_design.v"] --> YO["Yosys\nsynth"] YO --> LIB["lib-for-verilog\nskill"] LIB --> LIBFILE["cells.lib\nLiberty library"] LIBFILE --> CONV["convert-lib-to-json\nskill"] CONV --> JSONFILE["cells.json\nStructured JSON"] JSONFILE --> SCHEMA["liberty_json_schema.json\nSchema validation"] SCHEMA --> VALID["β Validated output"] JSONFILE --> ANAL["Python analysis\npandas, numpy, etc."] style RTL fill:#fff3e0,stroke:#e65100,color:#2e3440,stroke-width:3px style YO fill:#e3f2fd,stroke:#1565c0,color:#2e3440,stroke-width:3px style LIB fill:#f3e5f5,stroke:#7b1fa2,color:#2e3440,stroke-width:3px style LIBFILE fill:#ffcdd2,stroke:#c62828,color:#2e3440,stroke-width:3px style CONV fill:#e3f2fd,stroke:#1565c0,color:#2e3440,stroke-width:3px style JSONFILE fill:#c8e6c9,stroke:#2e7d32,color:#2e3440,stroke-width:3px style SCHEMA fill:#fff3e0,stroke:#e65100,color:#2e3440,stroke-width:3px style VALID fill:#c8e6c9,stroke:#2e7d32,color:#2e3440,stroke-width:3px style ANAL fill:#eceff1,stroke:#455a64,color:#2e3440,stroke-width:3px
graph LR LIB["Liberty .lib"] --- JSON["JSON"] JSON --- SCHEMA["Schema\nβ "] SCHEMA --- CONFIDENCE["Confidence\nπ"] CONFIDENCE --- LIB style LIB fill:#ffcdd2,stroke:#c62828,color:#2e3440,stroke-width:3px style JSON fill:#e3f2fd,stroke:#1565c0,color:#2e3440,stroke-width:3px style SCHEMA fill:#c8e6c9,stroke:#2e7d32,color:#2e3440,stroke-width:3px style CONFIDENCE fill:#fff3e0,stroke:#e65100,color:#2e3440,stroke-width:3px