layout: true class: typo, typo-selection --- count: false class: nord-dark, middle, center # ⏰ Timing Closure in VLSI Physical Design ### Setup, Hold, Skew & ECO Flows @luk036 👨‍💻 · 2026 📅 --- ### 📋 Agenda .pull-left[ **Part 1: STA Fundamentals** 🕐 - Setup & Hold Constraints - Slack & Critical Path Analysis **Part 2: Skew Optimization** 🔄 - Clock Skew Scheduling - Delay Padding **Part 3: Timing-Driven Flow** 🎯 - Timing-Driven Placement - ECO Flows ] .pull-right[ **Part 4: Advanced Topics** 🚀 - Statistical STA (SSTA) - ML for Timing Prediction **Part 5: Integration** 🔗 - Timing Closure Flow - Summary ] --- class: nord-light, middle, center ## Part 1: STA Fundamentals 🕐 --- ### What is Timing Closure? 🎯 > **Timing closure** is the process of ensuring that a digital circuit meets all timing constraints after physical design. .pull-left[ **Why it matters:** - Chip performance determined by critical path delay - Manufacturing variations affect timing - Late-stage timing fixes are expensive ] .pull-right[ .mermaid[ <pre> graph LR A[RTL Synthesis] --> B[Physical Design] B --> C[STA] C --> D{Timing Met?} D -->|No| E[Optimize] E --> B D -->|Yes| F[Signoff] style A fill:#e3f2fd,stroke:#1565c0,color:#2e3440,stroke-width:3px style B fill:#c8e6c9,stroke:#2e7d32,color:#2e3440,stroke-width:3px style C fill:#f3e5f5,stroke:#7b1fa2,color:#2e3440,stroke-width:3px style D fill:#ffcdd2,stroke:#c62828,color:#2e3440,stroke-width:3px style E fill:#fff3e0,stroke:#e65100,color:#2e3440,stroke-width:3px style F fill:#c8e6c9,stroke:#2e7d32,color:#2e3440,stroke-width:3px </pre> ] ] --- ### Static Timing Analysis (STA) Basics 🕐 **Setup Constraint** (max delay): $$ {\color{blue} T_{clk}} \geq {\color{orange} T_{ck\to q}} + {\color{green} T_{logic}} + {\color{red} T_{setup}} + {\color{darkmagenta} T_{skew}} $$ **Hold Constraint** (min delay): $$ {\color{orange} T_{ck\to q}} + {\color{green} T_{logic}} \geq {\color{red} T_{hold}} + {\color{darkmagenta} T_{skew}} $$ .pull-left[ | Term | Meaning | |------|---------| | ${\color{blue} T_{clk}}$ | Clock period | | ${\color{orange} T_{ck\to q}}$ | Clock-to-Q delay | | ${\color{green} T_{logic}}$ | Combinational logic delay | | ${\color{red} T_{setup}}$ | Setup time | | ${\color{red} T_{hold}}$ | Hold time | | ${\color{darkmagenta} T_{skew}}$ | Clock skew (${\color{orange} T_{ck2}} - {\color{blue} T_{ck1}}$) | ] .pull-right[ .mermaid[ <pre> graph LR subgraph "Launch Path" FF1[FF1] -->|T_ck→q| Comb[Logic] end subgraph "Capture Path" Comb -->|T_logic| FF2[FF2] end CLK[Clock] --> FF1 CLK --> FF2 style CLK fill:#fff3e0,stroke:#e65100,color:#2e3440,stroke-width:3px style FF1 fill:#e3f2fd,stroke:#1565c0,color:#2e3440,stroke-width:3px style Comb fill:#c8e6c9,stroke:#2e7d32,color:#2e3440,stroke-width:3px style FF2 fill:#e3f2fd,stroke:#1565c0,color:#2e3440,stroke-width:3px </pre> ] ] --- ### Setup & Hold Timing 🌉 .pull-left[ **Setup Violation** → Reduce logic delay: - Gate sizing (up-size critical gates) - Buffer insertion - Logic restructuring - Threshold voltage (VT) swapping **Hold Violation** → Increase delay: - Buffer insertion (delay padding) - Gate down-sizing - Route detour ] .pull-right[ .mermaid[ <pre> flowchart TD subgraph "Setup Fixes" A[Gate Sizing] --> A1[Faster cells] B[Buffer Insertion] --> B1[Split long wires] C[VT Swap] --> C1[Lower Vt = faster] D[Logic Restructure] --> D1[Reduce logic depth] end subgraph "Hold Fixes" E[Delay Padding] --> E1[Add buffers] F[Down-size] --> F1[Slower cells] G[Detour] --> G1[Longer wires] end style A fill:#c8e6c9,stroke:#2e7d32,color:#2e3440,stroke-width:3px style B fill:#c8e6c9,stroke:#2e7d32,color:#2e3440,stroke-width:3px style C fill:#c8e6c9,stroke:#2e7d32,color:#2e3440,stroke-width:3px style D fill:#c8e6c9,stroke:#2e7d32,color:#2e3440,stroke-width:3px style E fill:#fff3e0,stroke:#e65100,color:#2e3440,stroke-width:3px style F fill:#fff3e0,stroke:#e65100,color:#2e3440,stroke-width:3px style G fill:#fff3e0,stroke:#e65100,color:#2e3440,stroke-width:3px </pre> ] ] --- ### Slack and Critical Path 📊 **Slack**: The margin by which a timing constraint is met (positive) or violated (negative) $$ {\color{green} \text{Slack}} = {\color{blue} \text{Required Time}} - {\color{red} \text{Arrival Time}} $$ .pull-left[ - **Positive Slack** ✅ — Timing is met - **Negative Slack** ❌ — Violation, needs fixing - **Worst Negative Slack (WNS)**: Most critical violation - **Total Negative Slack (TNS)**: Sum of all violations - **Critical Path**: Path with least positive / most negative slack ] .pull-right[ .mermaid[ <pre> graph LR subgraph "Critical Path" P1[Path 1] -->|slack=+0.05ns| OK1[✅] P2[Path 2] -->|slack=-0.12ns| FIX[❌ Fix!] P3[Path 3] -->|slack=+0.30ns| OK2[✅] end style FIX fill:#ffcdd2,stroke:#c62828,color:#2e3440,stroke-width:3px style P2 fill:#ffcdd2,stroke:#c62828,stroke-width:3px </pre> ] ] --- class: nord-light, middle, center ## Part 2: Skew Optimization 🔄 --- ### Clock Skew: Friend or Foe? 🤔 **Traditional view**: Skew is bad — zero-skew trees minimize it. **Modern view**: Useful skew can improve timing! .pull-left[ **Positive skew** (data and clock flow in same direction): $$ {\color{darkmagenta} T_{skew}} = {\color{orange} T_{ck2}} - {\color{blue} T_{ck1}} > 0 $$ - Helps setup (more time for logic) - Hurts hold (less time for data stability) **Negative skew** (opposite direction): - Hurts setup - Helps hold ] .pull-right[ .mermaid[ <pre> graph TD subgraph "Useful Skew Example" CLK[Clock Source] CLK -->|T_ck1| FF1[FF1] CLK -->|T_ck2| FF2[FF2] FF1 -->|Data Path| FF2 end Note[Skew = T_ck2 - T_ck1] style CLK fill:#fff3e0,stroke:#e65100,color:#2e3440,stroke-width:3px style FF1 fill:#e3f2fd,stroke:#1565c0,color:#2e3440,stroke-width:3px style FF2 fill:#e3f2fd,stroke:#1565c0,color:#2e3440,stroke-width:3px style Note fill:#f3e5f5,stroke:#7b1fa2,color:#2e3440,stroke-width:3px </pre> ] ] --- ### Clock Skew Scheduling 🔄 Formulated as a linear programming (LP) problem: **Variables**: ${\color{orange} s_i}$ = clock arrival time at flip-flop $i$ **Constraints** (for each path $i \to j$): Setup: $$ {\color{green} s_j} - {\color{orange} s_i} \leq {\color{blue} T_{clk}} - {\color{red} D_{max}(i,j)} $$ Hold: $$ {\color{green} s_j} - {\color{orange} s_i} \geq -{\color{red} D_{min}(i,j)} $$ **Objective**: Minimize total negative slack or maximize yield > 📖 See: [Clock Skew Scheduling](../algo4dfm/css_under_pv.html) for details --- ### Delay Padding ⏳ When hold violations remain after useful skew optimization: - **Delay Padding**: Insert buffers or delay cells into short paths - **Goal**: Increase path delay to meet hold constraints .pull-left[ **Trade-offs**: - Increased power consumption - Area overhead - Potential setup degradation **Algorithms**: - Greedy padding (fix worst violators first) - LP-based optimal padding - Sensitivity-guided padding ] .pull-right[ .mermaid[ <pre> flowchart LR subgraph "Before Padding" FF1a[FF1] -->|1.2ns| FF2a[FF2] Note1[Hold slack: -0.3ns ❌] end subgraph "After Padding" FF1b[FF1] -->|+0.4ns| Buf[Buffer] -->|1.2ns| FF2b[FF2] Note2[Hold slack: +0.1ns ✅] end style FF1a fill:#ffcdd2,stroke:#c62828,stroke-width:3px style FF2a fill:#ffcdd2,stroke:#c62828,stroke-width:3px style Note1 fill:#ffcdd2,stroke:#c62828,color:#2e3440,stroke-width:3px style FF1b fill:#c8e6c9,stroke:#2e7d32,stroke-width:3px style Buf fill:#e3f2fd,stroke:#1565c0,color:#2e3440,stroke-width:3px style FF2b fill:#c8e6c9,stroke:#2e7d32,stroke-width:3px style Note2 fill:#c8e6c9,stroke:#2e7d32,color:#2e3440,stroke-width:3px </pre> ] > 📖 See: [delay_padding.md](../algo4dfm/delay_padding.md) ] --- class: nord-light, middle, center ## Part 3: Timing-Driven Flow 🎯 --- ### Timing-Driven Placement 🎯 Traditional placement minimizes wirelength. Timing-driven placement additionally considers timing criticality. .pull-left[ **Techniques**: 1. **Net Weighting**: Assign higher weights to critical nets 2. **Bound Constraints**: Keep critical cells close 3. **Replication**: Duplicate logic to reduce fanout 4. **Incremental Placement**: Local moves for timing fix ] .pull-right[ .mermaid[ <pre> flowchart TD Input[Netlist + Timing Constraints] Input --> Weight[Assign Net Weights] Weight --> Place[Analytical Placement] Place --> STA[STA] STA --> Check{Timing OK?} Check -->|No| Weight Check -->|Yes| Output[Legal Placement] style Input fill:#fff3e0,stroke:#e65100,color:#2e3440,stroke-width:3px style Weight fill:#e3f2fd,stroke:#1565c0,color:#2e3440,stroke-width:3px style Place fill:#e3f2fd,stroke:#1565c0,color:#2e3440,stroke-width:3px style STA fill:#f3e5f5,stroke:#7b1fa2,color:#2e3440,stroke-width:3px style Check fill:#ffcdd2,stroke:#c62828,color:#2e3440,stroke-width:3px style Output fill:#c8e6c9,stroke:#2e7d32,color:#2e3440,stroke-width:3px </pre> ] ] --- ### ECO Flows for Timing Closure 🔧 **Engineering Change Order (ECO)** — Late-stage timing fixes with minimal layout changes. .pull-left[ **ECO Types**: - **Pre-mask ECO**: Gate-level netlist changes before mask generation - **Post-mask ECO**: Metal-only fixes (spin) - **Buffer ECO**: Insert/remove buffers only **ECO Operations**: - Gate sizing (VT swap, drive strength) - Buffer insertion/removal - Layer assignment - Spare cell utilization ] .pull-right[ .mermaid[ <pre> graph LR subgraph "Timing ECO Flow" G[Gate-level Netlist] P[Physical Design] STA[STA Results] ECO[ECO Engine] G --> ECO P --> ECO STA --> ECO ECO -->|Minimal changes| New[Updated Layout] end style G fill:#e3f2fd,stroke:#1565c0,color:#2e3440,stroke-width:3px style P fill:#c8e6c9,stroke:#2e7d32,color:#2e3440,stroke-width:3px style STA fill:#f3e5f5,stroke:#7b1fa2,color:#2e3440,stroke-width:3px style ECO fill:#fff3e0,stroke:#e65100,color:#2e3440,stroke-width:3px style New fill:#c8e6c9,stroke:#2e7d32,color:#2e3440,stroke-width:3px </pre> ] ] --- class: nord-light, middle, center ## Part 4: Advanced Topics 🚀 --- ### Statistical Static Timing Analysis (SSTA) 📊 At advanced nodes, deterministic STA is insufficient due to process variations. .pull-left[ **Key Concepts**: - **Corner-based STA**: SS, TT, FF corners — pessimistic - **SSTA**: Treat delays as random variables - **Parametric yield**: Probability circuit meets timing **Challenges**: - Spatial correlation of variations - Non-Gaussian distributions (log-normal, GEV) - Computational complexity ] .pull-right[ .mermaid[ <pre> flowchart TD subgraph "Delay Distribution" PDF[Probability Density] Mean[Mean Delay] Sigma[σ = Variation] end subgraph "SSTA Approaches" P1[Parametric: First-order] P2[Monte Carlo: Accurate but slow] P3[Extreme Value: GEV for max] end style PDF fill:#e3f2fd,stroke:#1565c0,stroke-width:3px style Mean fill:#e3f2fd,stroke:#1565c0,color:#2e3440,stroke-width:3px style Sigma fill:#e3f2fd,stroke:#1565c0,color:#2e3440,stroke-width:3px style P1 fill:#c8e6c9,stroke:#2e7d32,stroke-width:3px style P2 fill:#fff3e0,stroke:#e65100,stroke-width:3px style P3 fill:#ffcdd2,stroke:#c62828,stroke-width:3px </pre> ] See also: [GEV.pdf](../algo4dfm/GEV.pdf), [unimodal](../algo4dfm/unimodal.html) ] --- ### Machine Learning for Timing Prediction 🤖 Modern ML approaches to accelerate timing closure: .pull-left[ **Applications**: - **Path delay prediction**: Replace slow SPICE with ML models - **Critical path identification**: Rank paths by criticality - **Gate sizing guidance**: Predict optimal cell choices - **Congestion-aware timing**: Correlate routing with delay **Popular Models**: - Gradient boosting (XGBoost, LightGBM) - Graph neural networks (GNNs) for netlist graphs - Transfer learning across designs ] .pull-right[ .mermaid[ <pre> flowchart TD Data[Design Data] --> Feat[Feature Extraction] Feat --> Model[ML Model] Model --> Pred[Delay Prediction] Pred --> Opt[Optimization] Opt -->|Feedback| Data style Model fill:#e3f2fd,stroke:#1565c0,color:#2e3440,stroke-width:3px style Pred fill:#c8e6c9,stroke:#2e7d32,color:#2e3440,stroke-width:3px </pre> ] ] --- class: nord-light, middle, center ## Part 5: Integration & Summary 🔗 --- ### Timing Closure Flow: Putting It All Together 🔄 .pull-left[ .mermaid[ <pre> graph TD Start[Physical Design] Start --> STA1[STA] STA1 --> Check1{Setup OK?} Check1 -->|No| US[Useful Skew Opt] US --> TS[Timing-Driven Placement] TS --> GS[Gate Sizing] GS --> Check2{Hold OK?} Check2 -->|No| DP[Delay Padding] DP --> STA2[STA Re-check] STA2 --> Final{All Met?} Final -->|No| ECO[ECO Flow] ECO --> STA2 Final -->|Yes| Signoff[Signoff] style Start fill:#fff3e0,stroke:#e65100,color:#2e3440,stroke-width:3px style STA1 fill:#f3e5f5,stroke:#7b1fa2,color:#2e3440,stroke-width:3px style Check1 fill:#ffcdd2,stroke:#c62828,color:#2e3440,stroke-width:3px style US fill:#e3f2fd,stroke:#1565c0,color:#2e3440,stroke-width:3px style TS fill:#e3f2fd,stroke:#1565c0,color:#2e3440,stroke-width:3px style GS fill:#e3f2fd,stroke:#1565c0,color:#2e3440,stroke-width:3px style Check2 fill:#ffcdd2,stroke:#c62828,color:#2e3440,stroke-width:3px style DP fill:#fff3e0,stroke:#e65100,color:#2e3440,stroke-width:3px style STA2 fill:#f3e5f5,stroke:#7b1fa2,color:#2e3440,stroke-width:3px style Final fill:#ffcdd2,stroke:#c62828,color:#2e3440,stroke-width:3px style ECO fill:#fce4ec,stroke:#ad1457,color:#2e3440,stroke-width:3px style Signoff fill:#c8e6c9,stroke:#2e7d32,color:#2e3440,stroke-width:3px </pre> ] ] .pull-right[ **Key Takeaways**: - Timing closure is **iterative** - Earlier fixes are cheaper - Useful skew helps both setup and hold - ML is transforming timing prediction - **Start early, check often** ⏰ ] --- ### Summary 📝 .pull-left[ **What We Covered:** 1. **STA fundamentals**: Setup, hold, slack 2. **Useful skew**: LP-based scheduling 3. **Delay padding**: Fixing hold violations 4. **Timing-driven placement**: Criticality-aware 5. **ECO flows**: Minimal-change fixes 6. **SSTA**: Statistical variation awareness 7. **ML for timing**: Data-driven prediction ] .pull-right[ **Key References:** - Kahng et al., _VLSI Physical Design: From Graph Partitioning to Timing Closure_ - Sapatnekar, _Timing_ - Alpert et al., "What Makes a Design Difficult to Close" (DAC 2010) - [Clock Skew Scheduling](../algo4dfm/css_under_pv.html) - [Delay Padding](../algo4dfm/delay_padding.md) ] --- count: false class: nord-dark, middle, center # 🙋 Q&A ### Questions? Discussion? 💬 --- count: false class: nord-dark, middle, center # 👏 Thank You ### Timing Closure in VLSI Physical Design Slides built with Remark.js 🎉 | KaTeX 📐 | Mermaid 🧩 | Nord Theme 🌙