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Csd 1.1.4; VERSION ${PROJECT_VERSION}
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Generate Verilog code for CSD multiplier. More...
#include <string>#include <vector>
Go to the source code of this file.
Classes | |
| struct | csd::MultiplierSpec |
| Specification for a single CSD multiplier coefficient. More... | |
Namespaces | |
| namespace | csd |
Functions | |
| auto | csd::generate_csd_multiplier (const std::string &csd_str, int input_width, int max_power) -> std::string |
| Generate Verilog code for a single CSD multiplier module. | |
| auto | csd::generate_csd_multipliers (const std::vector< MultiplierSpec > &coeffs, const std::string &module_name="csd_filter") -> std::string |
| Generate Verilog for multiple CSD multipliers with cross-CSE. | |
Generate Verilog code for CSD multiplier.
Translates a Canonical Signed Digit (CSD) string into a Verilog hardware module that implements multiplication using only shift-and-add/subtract operations - no actual multipliers needed. Each non-zero CSD digit becomes a shifted term, and the terms are summed.
Example: csd = "+00-00+0" -> result = x_shift7 - x_shift4 + x_shift1